Datasheet

Section 2 CPU
REJ09B0465-0300 Rev. 3.00 Page 35 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
SP (ER7)
Free area
Stack area
Figure 2.6 Stack
2.4.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched for read, the least significant PC bit is regarded as 0.)
2.4.3 Extended Control Register (EXR)
EXR is an 8-bit register that can be operated by the LDC, STC, ANDC, ORC, and XORC
instructions. When an instruction other than STC is executed, all interrupts including NMI are
masked in three states after the instruction is completed.
Bit Symbol Bit Name Description R/W
7 T Trace bit 0: Consecutively executes instructions.
1: Starts trace exception processing each time an
instruction is executed.
R/W
6 to 3 ⎯ Reserved These bits are always read as 1. ⎯
2 to 0 I2*
I1
I0
Interrupt
request mask
level 2 to 0
These bits specify interrupt request mask levels
(0 to 3). For details, see section 4, Interrupt
Controller.
R/W
Note: * The I2-bit is reserved in this product. The I2 bit is set to 1 if an interrupt is accepted, but
this does not affect the mask level for interrupt requests.