Datasheet

Section 16 Timer RD

REJ09B0465-0300 Rev. 3.00 Page 579 of 982

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

(6) Example of Buffer Operation Setting Procedure

Figure 16.43 shows an example of the buffer operation setting procedure.

[1] Designate GR as an input capture register or

output compare register by means of TRDIOR.

[2] Designate GR for buffer operation with bits

BFD1, BFC1, BFD0, or BFC0 in TRDMDR.

[3] Set the STR bit in TRDSTR to 1 to start the

count operation of TRDCNT.

[1]

[2]

[3]

Select GR function

Set buffer operation

Start count operation

Buffer operation

Figure 16.43 Example of Buffer Operation Setting Procedure

(7) Examples of Buffer Operation

Figure 16.44 shows an operation example in which GRA has been designated as an output

compare register, and buffer operation has been designated for GRA and GRC.

This is an example of TRDCNT operating as a periodic counter cleared by compare match B.

Pins FTIOA and FTIOB are set for toggle output by compare match A and B.

As buffer operation has been set, when compare match A occurs, the FTIOA pin performs toggle

outputs and the value in buffer register is simultaneously transferred to the general register. This

operation is repeated each time that compare match A occurs.