Datasheet

Section 16 Timer RD
Page 578 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
(2) When GR is an Input Capture Register
When an input capture occurs, the value in TRDCNT is transferred to GR and the value previously
stored in the general register is transferred to the buffer register.
This operation is illustrated in figure 16.42.
TRDCNT
Buffer register
General
register
Input capture
signal
Figure 16.42 Input Capture Buffer Operation
(3) PWM3 Mode
When compare match A0 occurs, the value of the buffer register is transferred to GR.
(4) Complementary PWM Mode
When the counter switches from counting up to counting down or vice versa, the value of the
buffer register is transferred to GR. Here, the value of the buffer register is transferred to GR in the
following timing:
• When TRDCNT_0 and GRA_0 are compared and their contents match
• When TRDCNT_1 underflows
(5) Reset Synchronous PWM Mode
When compare match A0 occurs, the value in the buffer register is transferred to GR.