Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 577 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.3.9 Buffer Operation
Buffer operation differs depending on whether GR has been designated for an input capture
register or an output compare register, or in reset synchronous PWM mode or complementary
PWM mode.
Table 16.10 shows the register combinations used in buffer operation.
Table 16.10 Register Combinations in Buffer Operation
General Register (GR) Buffer Register
GRA GRC
GRB GRD
(1) When GR is an Output Compare Register
When a compare match occurs, the value in the buffer register of the corresponding channel is
transferred to the general register.
This operation is illustrated in figure 16.41.
Buffer register Comparator TRDCNT
General
register
Compare match signal
Figure 16.41 Compare Match Buffer Operation