Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 575 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Figures 16.38 and 16.39 show examples of stopping operation of the counter in PWM3 mode,
when the CCLR2 to CCLR0 bits in TRDCR are set to clear TRDCNT_0 on GRA_0 compare
match. For details on PWM3 mode, see section 16.3.8, PWM3 Mode Operation.
The value of TRDCNT
Set to 1 by writing from the CPU
Cleared to 0 by GRA_0 compare match
H'FFFF
H'0000
GRA_0
GRA_1
GRB_0
GRB_1
FTIOA0
FTIOB0
STR0
CSTPN0
Counter cleared by GRA_0 compare match
Time
Figure 16.38 Example (1) of Stopping Operation of the Counter (in PWM3 Mode)
The value of TRDCNT
Counter cleared by GRA_0 compare match
H'FFFF
H'0000
GRA_0
GRA_1
GRB_0
GRB_1
FTIOA0
FTIOB0
STR0
CSTPN0
High
Time
Set to 1 by writing from the CPU Cleared to 0 by writing from the CPU
Figure 16.39 Example (2) of Stopping Operation of the Counter (in PWM3 Mode)