Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 573 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
[1] Select the counter clock with bits TPSC2
to TPSC0 in TRDCR. When an external
clock is selected, select the external
clock edge with bits CKEG1 and CKEG0
in TRDCR.
[2] Use bits CCLR2 to CCLR0 in TRDCR to
select counter clearing source GRA_0.
[3] Select PWM mode 3 with bit PWM3 in
TRDFCR.
[4] Set output levels with bits TOB0 and
TOA0 in TRDOCR.
[5] Set the GR buffer operation with bits
BFC0, BFC1, BFD0, and BFD1 in
TRDMDR.
[6] Set a cycle in GRA. Set the duty cycle in
other GR registers.
[7] Enable or disable the timer output by
TRDOER1.
[8] Set the STR bit in TRDSTR to 1 and start
the counter operation.
[1]
PWM mode 3
[2]
[3]
Select counter clock
[4]
Select counter clearing source
Set PWM mode 3
[5]
[6]
Select buffer operation
[7]
Set GR
[8]Start counter operation
Enable waveform output
<PWM mode 3>
Set output level
Figure 16.36 Flowchart of Setting in PWM3 Mode