Datasheet

Section 16 Timer RD
Page 572 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 16.9 Pin Configuration in PWM3 Mode and GR Registers
Channel Pin Name Input/Output
Compare Match
Register Buffer Register
GRA_0 GRC_0 FTIOA0
GRA_1 GRC_1
GRB_0 GRD_0 FTIOB0
Output
GRB_1 GRD_1
FTIOC0
0
FTIOD0
FTIOA1
FTIOB1
FTIOC1
1
FTIOD1
I/O General I/O port General I/O port
FTIOA0
Compare match signal
FTIOB0
Output
control
TRDCNT_0
Comparator
GRA_0
Comparator
GRB_0
GRD_0
Comparator
Comparator
GRB_1
Compare match signal
Compare match signal
Compare match signal
Output
control
GRA_1
GRC_1
GRC_0
GRD_1
Figure 16.35 Block Diagram in PWM3 Mode