Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 569 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
In complementary PWM mode, when the counter switches from up-counter to down-counter or
vice versa, TRDCNT_0 and TRDCNT_1 overshoots or undershoots, respectively. In this case, the
conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual
settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings
are shown in figures 16.33 and 16.34.
GR
Buffer transfer
signal
Set to 1.
Flag is not set.
Transferred
to buffer
Not transferred
to buffer
N+1
GRA_0
TRDCNT
N
N-1 N-1N
N
IMFA
Figure 16.33 Timing of Overshooting
H'FFFFH'0001 H'0001H'0000H'0000
GR
UDF
OVF
TRDCNT
Buffer transfer
signal
Set to 1.
Flag is not set.
Transferred
to buffer
Not transferred
to buffer
Figure 16.34 Timing of Undershooting