Datasheet

Section 16 Timer RD
Page 568 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Figure 16.32 shows an example of PWM waveform output with 0% duty and 100% duty in
complementary PWM mode (for one phase).
In this figure, GRB_0 is set to a value equal to or greater than GRA_0 and H'0000. The waveform
with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty
cycles can easily be changed, including the above settings, during operation. For details on buffer
operation, see section 16.3.9, Buffer Operation.
GRA_0
H'0000
FTIOB0
FTIOD0
GRA_0
(b) When duty is 100%
100% duty
TRDCNT values
TRDCNT values
Time
Time
0% duty
(a) When duty is 0%
GRB_0
H'0000
FTIOB0
FTIOD0
GRB_0
Figure 16.32 Example of Complementary PWM Mode Operation (2)