Datasheet

Section 16 Timer RD

REJ09B0465-0300 Rev. 3.00 Page 565 of 982

Sep 17, 2010

H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group

16.3.7 Complementary PWM Mode

Three PWM waveforms for non-overlapped normal and counter phases are output by combining

channels 0 and 1.

In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become

PWM-output pins automatically. TRDCNT_0 and TRDCNT_1 perform an increment or

decrement operation. Tables 16.7 and 16.8 show the output pins and register settings in

complementary PWM mode, respectively.

Figure 16.29 shows the example of complementary PWM mode setting procedure.

Table 16.7 Output Pins in Complementary PWM Mode

Channel Pin Name Input/Output Pin Function

0 FTIOC0 Output Toggle output in synchronous with PWM cycle

0 FTIOB0 Output PWM output 1

0 FTIOD0 Output PWM output 1 (counter-phase waveform non-

overlapped with PWM output 1)

1 FTIOA1 Output PWM output 2

1 FTIOC1 Output PWM output 2 (counter-phase waveform non-

overlapped with PWM output 2)

1 FTIOB1 Output PWM output 3

1 FTIOD1 Output PWM output 3 (counter-phase waveform non-

overlapped with PWM output 3)

Table 16.8 Register Settings in Complementary PWM Mode

TRDCNT_0 Initial setting of non-overlapped periods (non-overlapped periods are differences

with TRDCNT_1)

TRDCNT_1 Initial setting of H'0000

GRA_0 Sets (upper limit value – 1) of TRDCNT_0

GRB_0 Set a changing point of the PWM waveform output from pins FTIOB0 and

FTIOD0.

GRA_1 Set a changing point of the PWM waveform output from pins FTIOA1 and

FTIOC1.

GRB_1 Set a changing point of the PWM waveform output from pins FTIOB1 and

FTIOD1.