Datasheet

Section 16 Timer RD
Page 562 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
[1] Clear bit STR0 in TRDSTR to 0 and stop the
counter operation of TRDCNT_0. Set reset
synchronous PWM mode after TRDCNT_0
stops.
[2] Select the counter clock with bits TPSC2 to
TPSC0 in TRDCR. When an external clock
is selected, select the external clock edge
with bits CKEG1 and CKEG0 in TRDCR.
[3] Use bits CCLR2 to CCLR0 in TRDCR to
select counter clearing source GRA_0.
[4] Select the reset synchronous PWM mode
with bits CMD1 and CMD0 in TRDFCR.
FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1
become PWM output pins automatically.
[5] Set TRDCNT_0 as H'0000. TRDCNT_1
does not need to be set.
[6] GRA_0 is a cycle register. Set a cycle for
GRA_0. Set the changing point timing of the
PWM output waveform for GRB_0, GRA_1,
and GRB_1.
[7] Enable or disable the timer output by
TRDOER1.
[8] Set the STR bit in TRDSTR to 1 and start
the counter operation.
[1]
Reset synchronous PWM mode
[2]
Stop counter operation
[3]
Select counter clock
[4]
Select counter clearing source
Set reset synchronous PWM mode
[5]
[6]
Set TRDCNT
[7]
Set GR
[8]
Start counter operation
Enable waveform output
<Reset synchronous PWM mode>
Figure 16.26 Example of Reset Synchronous PWM Mode Setting Procedure