Datasheet

Section 16 Timer RD
Page 536 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.3 Operation
Timer RD has the following operating modes.
Timer mode operation
Enables output compare and input capture functions by setting the IOA2 to IOA0 and IOB2 to
IOB0 bits in TRDIORA and the IOC3 to IOC0 and IOD3 to IOD0 bits in TRDIORC
PWM mode operation
Enables PWM mode operation by setting TRDPMR
PWM3 mode operation
Enables PWM3 mode operation by setting the PWM3 bit in TRDFCR
Reset synchronous PWM mode operation
Enables reset synchronous PWM mode operation by setting the CMD1 and CMD0 bits in
TRDFCR
Complementary PWM mode operation
Enables complementary PWM mode operation by setting the CMD1 and CMD0 bits in
TRDFCR
The following tables show the operating modes of the FTIOA0 to FTIOD0 and FTIOA1 to
FTIOD1 pins set by the appropriate bits in the registers mentioned above. Set 1 to the PMR bits
corresponding to the pins allocated by the PMC.