Datasheet

Section 16 Timer RD
Page 534 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.2.16 Timer RD Digital Filtering Function Select Register (TRDDF)
Address:
Bit:
Value after reset:
b7
0
b6
0
b5
⎯
0
b4
⎯
0
b3
DFD
0
b2
DFC
0
b1
DFB
0
b0
DFA
0
H'FFFFCA, H'FFFFD1
DFCK[1:0]
Bit Symbol Bit Name Description R/W
7, 6 DFCK[1:0] Digital filter clock
select
00: φ/32
01: φ/8
10: φ
11: Clock specified by bits TPSC2 to TPSC0 in
TRDCR
R/W
5, 4 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
3 DFD Digital filter
function D
0: Disables the digital filter for the FTIOD pin
1: Enables the digital filter for the FTIOD pin
R/W
2 DFC Digital filter
function C
0: Disables the digital filter for the FTIOC pin
1: Enables the digital filter for the FTIOC pin
R/W
1 DFB Digital filter
function B
0: Disables the digital filter for the FTIOB pin
1: Enables the digital filter for the FTIOB pin
R/W
0 DFA Digital filter
function A
0: Disables the digital filter for the FTIOA pin
1: Enables the digital filter for the FTIOA pin
R/W
Note: The setting in this register is valid on the corresponding pin when the FTIOA to FTIOD
inputs are enabled by TRDIORA and TRDIORC.
Timer RD has two TRDDF registers, one for each channel.