Datasheet

Section 16 Timer RD
Page 532 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.2.14 Timer RD Interrupt Enable Register (TRDIER)
Address:
Bit:
Value after reset:
b7
⎯
1
b6
⎯
1
b5
⎯
1
b4
OVIE
0
b3
IMIED
0
b2
IMIEC
0
b1
IMIEB
0
b0
IMIEA
0
H'FFFFC8, H'FFFFCF
Bit Symbol Bit Name Description R/W
7 to 5 ⎯ Reserved These bits are read as 1. The write value should be 1. ⎯
4 OVIE Overflow interrupt
enable
0: Interrupt requests (OVI) by OVF or UDF flag are
disabled.
1: Interrupt requests (OVI) by OVF or UDF flag are
enabled.
R/W
3 IMIED Input capture/
compare match
interrupt enable D
0: Interrupt requests (IMID) by IMFD flag are disabled.
1: Interrupt requests (IMID) by IMFD flag are enabled.
R/W
2 IMIEC Input capture/
compare match
interrupt enable C
0: Interrupt requests (IMIC) by IMFC flag are disabled.
1: Interrupt requests (IMIC) by IMFC flag are enabled.
R/W
1 IMIEB Input capture/
compare match
interrupt enable B
0: Interrupt requests (IMIB) by IMFB flag are disabled.
1: Interrupt requests (IMIB) by IMFB flag are enabled.
R/W
0 IMIEA Input capture/
compare match
interrupt enable A
0: Interrupt requests (IMIA) by IMFA flag are disabled.
1: Interrupt requests (IMIA) by IMFA flag are enabled.
R/W
Timer RD has two TRDIER registers, one for each channel.