Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 523 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.2.11 Timer RD Control Register (TRDCR)
Address:
Bit:
Value after reset:
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
TPSC[2:0]
0
b0
0
H'FFFFCA, H'FFFFD1
CCLR[2:0] CKEG[1:0]
Bit Symbol Bit Name Description R/W
7 to 5 CCLR[2:0] Counter clear
2 to 0
000: Disables TRDCNT clearing
001: Clears TRDCNT by GRA compare match/input
capture*
1
010: Clears TRDCNT by GRB compare match/input
capture*
1
011: Synchronization clear; Clears TRDCNT in
synchronous with counter clearing of the other
channel's timer*
2
100: Disables TRDCNT clearing
101: Clears TRDCNT by GRC compare match/input
capture*
1
110: Clears TRDCNT by GRD compare match/input
capture*
1
111: Synchronization clear; Clears TRDCNT in
synchronous with counter clearing of the other
channel's timer*
2
R/W
4, 3 CKEG[1:0] Clock edge
1 and 0
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
R/W