Datasheet

Section 16 Timer RD
Page 522 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
GR are 16-bit registers. Timer RD has eight general registers (GR), four for each channel. The GR
registers are dual function 16-bit readable/writable registers, functioning as either output compare
or input capture registers. Functions can be switched by TRDIORA and TRDIORC.
The values in GR and TRDCNT are constantly compared with each other when the GR registers
are used as output compare registers. When the both values match, the IMFA to IMFD flags in
TRDSR are set to 1. Compare match outputs can be selected by TRDIORA and TRDIORC.
When the GR registers are used as input capture registers, the TRDCNT value is stored after
detecting external signals. At this point, IMFA to IMFD flags in the corresponding TRDSR are set
to 1. Detection edges for input capture signals can be selected by TRDIORA and TRDIORC.
When PWM mode, complementary PWM mode, or reset synchronous PWM mode is selected, the
values in TRDIORA and TRDIORC are ignored. Upon reset, the GR registers are set as output
compare registers (no output) and initialized to H'FFFF. The GR registers cannot be accessed in 8-
bit units; they must always be accessed as a 16-bit unit.