Datasheet

Section 16 Timer RD
Page 520 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
0 ADTRGA0E A/D
conversion
start trigger A0
enable
0: A/D conversion start trigger is not generated by
compare match of GRA_0
1: A/D conversion start trigger is generated by
compare match of GRA_0
R/W
TRDADCR selects the trigger source to start A/D conversion. A/D conversion start trigger is
generated by a corresponding compare match.
16.2.9 Timer RD Counter (TRDCNT)
H'FFFFB0, H'FFFFBA
b15
0
b14
0
b13
0
b12
0
b11
0
b10
0
b9
0
b8
0
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
Address:
Bit:
Value after reset:
Timer RD has two TRDCNT counters (TRDCNT_0 and TRDCNT_1), one for each channel. The
TRDCNT counters are 16-bit readable/writable registers that increment/decrement according to
input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TRDCR. TRDCNT_0 and
TRDCNT_1 increment/decrement in complementary PWM mode while they only increment in
other modes.
The TRDCNT counters are initialized to H'0000 by compare matches with corresponding GRA,
GRB, GRC, or GRD, or input captures to GRA, GRB, GRC, or GRD (counter clearing function).
When the TRDCNT counters overflow, an OVF flag in TRDSR for the corresponding channel is
set to 1. When TRDCNT_1 underflows, an UDF flag in TRDSR is set to 1. The TRDCNT
counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.