Datasheet

Section 16 Timer RD
Page 516 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
5 EB1 Master enable
B1
0: FTIOB1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_1 settings
1: FTIOB1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_1 settings
(FTIOB1 pin is operated as an I/O port).
R/W
4 EA1 Master enable
A1
0: FTIOA1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_1 settings
1: FTIOA1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_1 settings
(FTIOA1 pin is operated as an I/O port).
R/W
3 ED0 Master enable
D0
0: FTIOD0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_0 settings
1: FTIOD0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_0 settings
(FTIOD0 pin is operated as an I/O port).
R/W
2 EC0 Master enable
C0
0: FTIOC0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_0 settings
1: FTIOC0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_0 settings
(FTIOC0 pin is operated as an I/O port).
R/W
1 EB0 Master enable
B0
0: FTIOB0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_0 settings
1: FTIOB0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_0 settings
(FTIOB0 pin is operated as an I/O port).
R/W
0 EA0 Master enable
A0
0: FTIOA0 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORA_0 settings
1: FTIOA0 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORA_0 settings
(FTIOA0 pin is operated as an I/O port).
R/W
TRDOER1 enables/disables the outputs for channel 0 and channel 1. When TRDOI is selected for
inputs, if a low level signal is input to TRDOI, the bits in TRDOER1 are set to 1 to disable the
output for timer RD.