Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 515 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
TRDCNT_0
Normal
phase
Counter
phase
Normal
phase
Counter
phase
Active level
Active level
Active level
Active level
Complementary PWM mode
Note: Write H'00 to TRDOCR to start initial outputs after stopping the counter.
Reset synchronous PWM mode
Initial
output
Initial
output
TRDCNT_1
Figure 16.4 Example of Outputs in Reset Synchronous PWM Mode
and Complementary PWM Mode
16.2.5 Timer RD Output Master Enable Register 1 (TRDOER1)
Address:
Bit:
Value after reset:
b7
ED1
1
b6
EC1
1
b5
EB1
1
b4
EA1
1
b3
ED0
1
b2
EC0
1
b1
EB0
1
b0
EA0
1
H'FFFFD6
Bit Symbol Bit Name Description R/W
7 ED1 Master enable
D1
0: FTIOD1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_1 settings
1: FTIOD1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_1 settings
(FTIOD1 pin is operated as an I/O port).
R/W
6 EC1 Master enable
C1
0: FTIOC1 pin output is enabled according to the
TRDPMR, TRDFCR, and TRDIORC_1 settings
1: FTIOC1 pin output is disabled regardless of the
TRDPMR, TRDFCR, and TRDIORC_1 settings
(FTIOC1 pin is operated as an I/O port).
R/W