Datasheet
Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 511 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
16.2.2 Timer RD Mode Register (TRDMDR)
Address:
Bit:
Value after reset:
b7
BFD1
0
b6
BFC1
0
b5
BFD0
0
b4
BFC0
0
b3
⎯
1
b2
⎯
1
b1
⎯
1
b0
SYNC
0
H'FFFFD3
Bit Symbol Bit Name Description R/W
7 BFD1 Buffer
operation D1
0: GRD_1 operates normally
1: GRB_1 and GRD_1 are used together for buffer
operation
R/W
6 BFC1 Buffer
operation C1
0: GRC_1 operates normally
1: GRA_1 and GRC_1 are used together for buffer
operation
R/W
5 BFD0 Buffer
operation D0
0: GRD_0 operates normally
1: GRB_0 and GRD_0 are used together for buffer
operation
R/W
4 BFC0 Buffer
operation C0
0: GRC_0 operates normally
1: GRA_0 and GRC_0 are used together for buffer
operation
R/W
3 to 1 ⎯ Reserved These bits are read as 1. The write value should be
1.
⎯
0 SYNC Timer
synchronization
0: TRDCNT_1 and TRDCNT_0 operate as
independent timer counters
1: TRDCNT_1 and TRDCNT_0 operate
synchronously
TRDCNT_1 and TRDCNT_0 can be pre-set or
cleared synchronously.
R/W