Datasheet

Section 16 Timer RD
Page 500 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• High-speed access by the internal 16-bit bus
16-bit TRDCNT and GR registers can be accessed in high speed by a 16-bit bus interface
• Any initial timer output value can be set
• Output of the timer is disabled by external trigger
• Eleven interrupt sources
Four compare match/input capture interrupts and an overflow interrupt are available for each
channel. An underflow interrupt can be set for channel 1.