Datasheet

Section 16 Timer RD
REJ09B0465-0300 Rev. 3.00 Page 499 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Section 16 Timer RD
This LSI has two units of 16-bit timers (timer RD_0 and timer RD_1), each of which has two
channels (one unit for the H8S/20103 and H8S/20115 Groups). Table 16.1 lists the timer RD
functions, table 16.2 lists the channel configuration of timer RD, and figure 16.1 is a block
diagram of the entire timer RD. Block diagrams of channels 0 and 1 are shown in figures 16.2 and
16.3.
Timer RD_0 has the same functions as timer RD_1. Therefore, the unit number (_0 or _1) is not
explicitly mentioned in this section unless otherwise noted.
16.1 Features
• Capability to process up to eight inputs/outputs
• Eight general registers (GR): four registers for each channel
Independently assignable output compare or input capture functions
• Selection of six counter clock sources: five internal clocks (φ, φ/2, φ/4, φ/8, and φ/32) and an
external clock
• Seven selectable operating modes
⎯ Timer mode
Output compare function (Selection of 0 output, 1 output, or toggle output)
Input capture function (Rising edge, falling edge, or both edges)
⎯ Synchronous operation
Timer counters_0 and _1 (TRDCNT_0 and TRDCNT_1) can be written simultaneously.
Simultaneous clearing by compare match or input capture is possible.
⎯ PWM mode
Up to six-phase PWM output can be provided with desired duty ratio.
⎯ PWM3 mode
One-phase PWM output for non-overlapped normal and counter phases
⎯ Reset synchronous PWM mode
Three-phase PWM output for normal and counter phases
⎯ Complementary PWM mode
Three-phase PWM output for non-overlapped normal and counter phases
The A/D conversion start trigger can be set for PWM cycles.
⎯ Buffer operation
The input capture register can be consisted of double buffers.
The output compare register can automatically be modified.