Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 495 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.5 Usage Notes
The following types of contention or operation can occur in timer RC operation.
1. When the digital filtering function for input is not in use, the pulse width of the input clock
signal and the input capture signal must be at least three system clock (φ) cycles when the
CKS2 to CKS0 bits in TRCCR1 = B'0XX or B'10X; shorter pulses will not be detected
correctly.
2. Writing to registers is performed in the T2 state of a TRCCNT write cycle.
If counter clear signal occurs in the T2 state of a TRCCNT write cycle, clearing of the counter
takes priority and the write is not performed, as shown in figure 15.37. If the TRCCNT write
cycle contends with the TRCCNT counting-up, writing takes precedence.
3. TRCCNT may erroneously count up depends on the timing of switching internal clocks. The
count clock is generated by detecting the rising edge of the divided system clock (φ) when the
internal clock is selected. If clocks are switched as shown in figure 15.38, the change from the
low level of the previous clock to the high level of the new clock is considered as the rising
edge. In this case, TRCCNT counts up the clock erroneously.
4. If timer RC enters the module standby mode while an interrupt is being requested, the interrupt
request cannot be cleared. Before entering the module standby mode, disable interrupt
requests.
Counter clear
signal
Write signal
Address
φ
TRCCNT address
TRCCNT
TRCCNT write cycle
T1
T2
N
H'0000
Figure 15.37 Contention between TRCCNT Write and Clear