Datasheet

Section 15 Timer RC
Page 492 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.4.7 Timing of IMFA to IMFD Setting at Input Capture
The corresponding IMFA, IMFB, IMFC, or IMFD flag which functions as a general register is set
to 1 when an input capture occurs. Figure 15.34 shows the timing of the IMFA to IMFD flag
setting at input capture.
GRA to GRD
TRCCNT
Input capture
signal
φ
N
N
IMFA to IMFD
Figure 15.34 Timing of IMFA to IMFD Flag Setting at Input Capture