Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 491 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.4.6 Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) matches TRCCNT, the corresponding IMFA to
IMFD flag which is used as output compare register is set to 1.
The compare match signal is generated in the last state in which the values match (when TRCCNT
is updated from the matching count to the next count). Therefore, when TRCCNT matches a
general register (GRA, GRB, GRC, or GRD), the compare match signal is generated only after the
next TRCCNT clock pulse is input.
Figure 15.33 shows the timing of the IMFA to IMFD flag setting at compare match.
GRA to GRD
TRCCNT
TRCCNT input
clock
φ
N
N
N + 1
Compare match
signal
IMFA to IMFD
Figure 15.33 Timing of IMFA to IMFD Flag Setting at Compare Match