Datasheet

Section 15 Timer RC
Page 488 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.4.2 Output Compare Output Timing
The compare match signal is generated in the last state in which TRCCNT and GR match (when
TRCCNT changes from the matching value to the next value). When the compare match signal is
generated, the output value selected in TRCIOR is output on the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD).
When TRCCNT matches GR, the compare match signal is generated only after the next counter
clock pulse is input.
Figure 15.28 shows the output compare timing.
GRA to GRD
TRCCNT
TRCCNT input
clock
φ
N
N
N + 1
Compare
match signal
FTIOA to FTIOD
Figure 15.28 Output Compare Output Timing