Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 477 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
GRA
TRCCNT
φ
L
M
N
N N + 1 H'0000
M
Counter clear
signal by trigger
input
GRB
GRD
Figure 15.16 GRD and GRB Buffer Operating Timing in PWM2 Mode (2)
In PWM2 mode, a pulse with arbitrary pulse width and delay time to the TRGC input can be
output from the FTIOB pin
Figures 15.17 and 15.18 show these examples in PWM2 mode. In these examples, the falling edge
of the TRGC input is selected by TRCCR2 (setting the TCEG1 bit to 1 and clearing the TCEG0
bit to 0), TRCCNT continues counting-up on compare match A of GRA (clearing the CSTP bit in
TRCCR2 to 0), and GRD is set as the buffer register (setting the BUFEB bit in TRCMR to 1). The
initial value of the output signal is set to either 0 or 1 by TRCCR1 (clearing the TOB bit to 0 or
setting the TOB bit to 1), TRCCNT is cleared on compare match A (setting the CCLR bit in
TRCCR1 to 1), and the waveform is output from the FTIOB pin (clearing the PWM2 bit in
TRCMR to 0).
When the TOB bit in TRCCR1 is cleared to 0 with the PWM2 mode function, the input edge is
ignored while the FTIOB pin is driven high. Whereas, when the TOB bit is set to 1, the input edge
is ignored while the FTIOB pin is driven low. The transfer from GRD to GRB is carried out on a
compare match of GRA and the TRGC input. However, if the TRGC input is canceled due to the
change of the FTIOB level, the transfer from GRD to GRB is not carried out.