Datasheet

Section 15 Timer RC
Page 470 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.3.2 PWM Mode Operation
In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB,
GRC, and GRD as duty cycle registers. PWM waveforms are output from the FTIOB, FTIOC, and
FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register
functions as an output compare register automatically. The initial output level of each pin depends
on the settings in TRCCR1 and TRCCR2. Table 15.7 shows an example of the initial output level
of the FTIOB pin.
Table 15.7 Initial Output Level of FTIOB Pin
Bit TOB (TRCCR1) Bit POLB (TRCCR2) Initial Output Level
0 0 1
0 1 0
1 0 0
1 1 1
The output level of each pin is determined by the value of the corresponding PWM mode output
level control bit (POLB, POLC, or POLD) in TRCCR2. When POLB is 0, the FTIOB output pin is
set to 0 on compare match B, and set to 1 on compare match A, whereas when POLB is 1, the
FTIOB output pin is set to 1 on compare match B, and set to 0 on compare match A. When an
output pin is set to PWM mode, the settings in TRCIOR0 and TRCIOR1 are ignored. If the same
value is set in the cycle register and duty cycle register, output levels are not changed when a
compare match occurs.