Datasheet

Section 15 Timer RC
Page 462 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Each general register is a 16-bit readable/writable register that can function as either an output-
compare register or an input-capture register. The function is selected by settings in TRCIOR0 and
TRCIOR1.
When a general register is used as an input-compare register, its value is constantly compared with
the TRCCNT value. When the two values match (a compare match), the corresponding flag (the
IMFA, IMFB, IMFC, or IMFD bit) in TRCSR is set to 1. An interrupt request is generated at this
time, when the IMIEA, IMIEB, IMIEC, or IMIED bit in TRCIER is set to 1. A compare match
output can be selected in TRCIOR.
When a general register is used as an input-capture register, an external input-capture signal is
detected and the current TRCCNT value is stored in the general register. The corresponding flag
(the IMFA, IMFB, IMFC, or IMFD bit) in TRCSR is set to 1. If the corresponding interrupt-
enable bit (the IMIEA, IMIEB, IMIEC, or IMIED bit) in TRCIER is set to 1 at this time, an
interrupt request is generated. The edge of the input-capture signal is selected in TRCIOR.
GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA
and BUFEB in TRCMR.
For example, when GRA is set as an output-compare register and GRC is set as the buffer register
for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is
generated.
When GRA is set as an input-capture register and GRC is set as the buffer register for GRA, the
value in TRCCNT is transferred to GRA and the value in the buffer register GRA is transferred to
GRC whenever an input capture is generated.
GRA to GRD must be written or read in 16-bit units; 8-bit access is not allowed. GRA to GRD are
initialized to H'FFFF by a reset.