Datasheet
Section 15 Timer RC
Page 460 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.2.11 Timer RC Counter (TRCCNT)
b15
0
b14
0
b13
0
b12
0
b11
0
b10
0
b9
0
b8
0
H'FFFF80
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
Address:
Bit:
Value after reset:
TRCCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to
CKS0 in TRCCR1. TRCCNT can be cleared to H'0000 through a compare match of GRA by
setting the CCLR bit in TRCCR1 to 1. When TRCCNT overflows from H'FFFF to H'0000, the
OVF flag in TRCSR is set to 1. If the OVIE bit in TRCIER is set to 1 at this time, an interrupt
request is generated. TRCCNT must always be read from or written to in units of 16 bits; 8-bit
accesses are not allowed. The initial value of TRCCNT is H'0000.