Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 459 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.2.10 Timer RC A/D Conversion Start Trigger Control Register (TRCADCR)
b7
⎯
1
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
ADTRGAE
0
b2
ADTRGBE
0
b1
ADTRGCE
0
b0
ADTRGDE
0
H'FFFF93
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 to 4 ⎯ Reserved These bits are read as 1. The write value should
be 1.
⎯
3 ADTRGAE A/D conversion
start trigger A
enable
0: A/D conversion start trigger is not generated by
compare match of GRA
1: A/D conversion start trigger is generated by
compare match of GRA
R/W
2 ADTRGBE A/D conversion
start trigger B
enable
0: A/D conversion start trigger is not generated by
compare match of GRB
1: A/D conversion start trigger is generated by
compare match of GRB
R/W
1 ADTRGCE A/D conversion
start trigger C
enable
0: A/D conversion start trigger is not generated by
compare match of GRC
1: A/D conversion start trigger is generated by
compare match of GRC
R/W
0 ADTRGDE A/D conversion
start trigger D
enable
0: A/D conversion start trigger is not generated by
compare match of GRD
1: A/D conversion start trigger is generated by
compare match of GRD
R/W
TRCADCR selects the trigger source to start A/D conversion. A/D conversion start trigger is
generated by a corresponding compare match.