Datasheet

Section 15 Timer RC
Page 456 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
3 IOC3 I/O control C3 0: GRC is used as GR for the FTIOA pin
1: GRC is used as GR for the FTIOC pin
R/W
2 IOC2 I/O control C2 0: GRC functions as an output compare register
1: GRC functions as an input capture register
R/W
1, 0 IOC[1:0] I/O control C1
and C0
When IOC3 = 0,
00: No output on compare match
01: 0 output to the FTIOA pin on compare match of
GRC
10: 1 output to the FTIOA pin on compare match of
GRC
11: Toggle output to the FTIOA pin on compare
match of GRC
When IOC3 = 1 and IOC2 = 0,
00: No output on compare match
01: 0 output to the FTIOC pin on compare match of
GRC
10: 1 output to the FTIOC pin on compare match of
GRC
11: Toggle output to the FTIOC pin on compare
match of GRC
When IOC3 = 1 and IOC2 = 1,
00: Input capture to GRC at rising edge of the
FTIOC pin
01: Input capture to GRC at falling edge of the
FTIOC pin
1X: Input capture to GRC at rising and falling
edges of the FTIOC pin
R/W
[Legend]
X: Don't care.
Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings
in the IOA2 and IOB2 bits in TRCIOR0 and the IOC2 and IOD2 bits in TRCIOR1 of both
registers should be the same.
2. The setting of TRCIOR1 is invalid in PWM mode and PWM2 mode.