Datasheet

Section 15 Timer RC
Page 454 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
1, 0 IOA[1:0] I/O control A1
and A0
When IOA2 = 0,
00: No output on compare match
01: 0 output to the FTIOA pin on compare match of
GRA
10: 1 output to the FTIOA pin on compare match of
GRA
11: Toggle output to the FTIOA pin on compare
match of GRA
When IOA2 = 1,
00: Input capture to GRA at rising edge of the FTIOA
pin
01: Input capture to GRA at falling edge of the FTIOA
pin
1X: Input capture to GRA at rising and falling edges
of the FTIOA pin
R/W
[Legend]
X: Don't care.
Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings
in the IOA2 and IOB2 bits in TRCIOR0 and the IOC2 and IOD2 bits in TRCIOR1 of both
registers should be the same.
2. The setting of TRCIOR is invalid in PWM mode and PWM2 mode.
TRCIOR0 selects the functions of GRA and GRB, and specifies the functions of the FTIOA and
FTIOB pins.