Datasheet

Section 2 CPU
Page 22 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• High-speed operation
All frequently-used instructions are executed in one or two states
⎯ 8/16/32-bit register-register add/subtract: 1 state
⎯ 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B)
⎯ 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B)
⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W)
⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.W)
• Two CPU operating modes
⎯ Normal mode
⎯ Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
Selectable CPU clock speed
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MULXU MULXU.B Rs, Rd 3 12
MULXU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 13
MULXS.W Rs, ERd 5 21
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.