Datasheet

Section 15 Timer RC
Page 452 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
0 IMFA Input capture/
compare match
flag A
[Setting conditions]
• TRCCNT = GRA when GRA functions as an
output compare register.
• The TRCCNT value is transferred to GRA by
an input capture signal when GRA functions as
an input capture register.
[Clearing condition]
• Read IMFA when IMFA = 1, then write 0 in
IMFA.
The DTC is activated by an IMFA interrupt when
the DISEL bit in MRB of DTC is 0.
R/W