Datasheet

Section 15 Timer RC
Page 450 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.2.5 Timer RC Status Register (TRCSR)
b7
OVF
0
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
IMFD
0
b2
IMFC
0
b1
IMFB
0
b0
IMFA
0
H'FFFF8D
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 OVF Timer overflow flag 0: TRCCNT has not overflowed.
1: TRCCNT has overflowed.
[Setting condition]
• When TRCCNT overflows from H'FFFF to
H'0000.
[Clearing condition]
• Read OVF when OVF = 1, then write 0 in OVF.
R/W
6 to 4 ⎯ Reserved These bits are read as 1. The write value should
be 1.
⎯
3 IMFD Input capture/
compare match
flag D
[Setting conditions]
• TRCCNT = GRD when GRD functions as an
output compare register.
• The TRCCNT value is transferred to GRD by
an input capture signal when GRD functions as
an input capture register.
• TRCCNT = GRD when the PWMD bit is set to
1 or the PWM2 bit to 0 in TRCMR.
[Clearing conditions]
• Read IMFD when IMFD = 1, then write 0 in
IMFD.
• The DTC is activated by an IMFD interrupt and
the DISEL bit in MRB of DTC is 0.
R/W