Datasheet

Section 15 Timer RC
Page 448 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.2.3 Timer RC Control Register 2 (TRCCR2)
b7
0
b6
0
b5
CSTP
0
b4
⎯
1
b3
⎯
1
b2
POLD
0
b1
POLC
0
b0
POLB
0
H'FFFF90
TCEG[1:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7, 6 TCEG[1:0] TRGC input edge
select
00: A trigger input on TRGC is disabled.
01: The rising edge is selected.
10: The falling edge is selected.
11: Both edges are selected.
R/W
5 CSTP Count stop 0: TRCCNT counting up continues.
1: TRCCNT counting up is halted.
R/W
4, 3 ⎯ Reserved These bits are read as 1. The write value should
be 1.
⎯
2 POLD PWM mode output
level control D
0: The TRCIOD output is active low.
1: The TRCIOD output is active high.
R/W
1 POLC PWM mode output
level control C
0: The TRCIOC output is active low.
1: The TRCIOC output is active high.
R/W
0 POLB PWM mode output
level control B
0: The TRCIOB output is active low.
1: The TRCIOB output is active high.
R/W
• TCEG[1:0] bits (TRGC input edge select)
These bits select the input edge of the TRGC signal. This function is only enabled when the
PWM2 bit in TRCMR is set to 0.
• CSTP bit (count stop)
Specifies whether TRCCNT counting up is halted by the compare match A signal. This
function is enabled in all operating modes. To resume counting after counting has been
stopped on a compare match, set the CTS bit in the timer RC mode register (TRCMR) to 1.