Datasheet

Section 15 Timer RC
REJ09B0465-0300 Rev. 3.00 Page 445 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
15.2.1 Timer RC Mode Register (TRCMR)
b7
CTS
0
b6
⎯
1
b5
BUFEB
0
b4
BUFEA
0
b3
PWM2
1
b2
PWMD
0
b1
PWMC
0
b0
PWMB
0
H'FFFF8A
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 CTS Counter start 0: TRCCNT stops counting.
1: TRCCNT starts counting.
[Setting conditions]
• When 1 is written in CTS
• When the specified event is occurred after
ELOPA of the event link controller is selected
counting by timer RC.
[Clearing conditions]
• When 0 is written in CTS
• In PWM2 mode, when the CSTP bit in TRCCR2
is set to 1 and a compare match signal is
generated.
R/W
6 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯
5 BUFEB Buffer
operation B
0: GRD functions as an input capture/output
compare register
1: GRD functions as the buffer register for GRB
R/W
4 BUFEA Buffer
operation A
0: GRC functions as an input capture/output
compare register
1: GRC functions as the buffer register for GRA
R/W
3 PWM2 PWM2 mode 0: Timer RC functions in PWM2 mode.
The following settings are invalid: TRCIOR0,
TRCIOR1, and the PWMB, PWMC, and PWMD
bits in TRCMR.
1: Timer RC functions in timer mode or PWM mode.
The following settings are valid: TRCIOR0,
TRCIOR1, and the PWMB, PWMC, and PWMD
bits in TRCMR.
R/W