Datasheet

Section 14 Timer RB
Page 436 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
14.3.5 Timing at Which Values Take Effect in Prescaler or Counter Depending on TWRC
Bit
Depending on the value assigned to the TWRC bit in TRBMR, the timing at which the value
written to TRBPRE, TRBPR, or TRBSC during timer operation takes effect in the counter can
vary.
If TWRC is set to 1 and value is written only to the register, the counter value is updated between
cycles, thus preventing the occurrence of fractional cycles. In modes other than the timer mode,
TWRC should be set to 1.
Figure 14.5 shows operation examples on the prescaler and the counter when the value of TWRC
is 0 and 1.
If TCSTF is 1, even when TWRC is cleared to 0, any transfer to the prescaler or the counter is
performed in synchronization with the count source; therefore, the counter value is not updated
immediately after the execution of a write instruction.