Datasheet

Section 14 Timer RB
Page 434 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
14.3.4 Programmable Wait One-Shot Generation Mode
This mode outputs one-shot pulses from the TRBO pin after a fixed amount of time based on
either program or external trigger input. When a trigger is generated, beginning with that point in
time, pulses are output only once for any length of time set in TRBSC, after any length of time set
in TRBPR.
(1) Starting and Stopping Operation
The counting is started when 1 is written to the TOSST bit in TRBOCR or a valid trigger signal is
input to the TRGB pin after the TSTART bit in TRBCR is set to 1 and the TCSTF flag is set to 1.
For a trigger input, the pulse must be longer than one cycle of the clock source for counting.
The counting is stopped when reloading is performed with an underflow of the timer RB counter
during the secondary period counting, when 1 is written to the TOSSP bit in TRBOCR, or when 0
is written to the TSTART bit in TRBCR.
(2) Forced Termination of Operation
Writing 1 to the TSTOP bit in TRBCR stops the counting forcedly. When the counting is forcedly
stopped, the timer RB counter, the prescaler counter, and any associated flags are initialized.
(3) Interrupt Request
An interrupt request is generated on the underflow of the timer RB counter during the secondary
period counting.
(4) Reading and Writing Count Value
Reading TRBPRE and TRBTR reads count values from each register.
If a write is performed to TRBPRE, TRBPR, or TRBSC when counting is stopped, set values are
written to both the reload register and the counter.
If a write is performed to TRBPRE, TRBPR, or TRBSC during counting, data is written only to
the respective reload registers. The value written to TRBPRE takes effect in synchronization with
the underflow of the prescaler. The value written to TRBPR takes effect during the next one-shot
pulse.
After writing to TRBSC and TRBPR when TCSTF = 1 or TOSSTF = 0, if a write is successively
performed to TRBSC and then to TRBPR, allow an interval of 5 cycles of the clock source for
counting before writing 1 to the TOSST bit.
In this mode, TRBPRE or TRBPR should not be set to H'00.