Datasheet

Section 14 Timer RB
Page 428 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
14.2.8 Timer RB Primary Register (TRBPR)
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
H'FFFFA6
Bit:
Address:
Value after reset:
TRBPR is an 8-bit reload register that sets the cycle or primary period for the timer RB counter.
The timer RB counter consists of two registers, primary and secondary registers, and a counter.
The primary register and counter are assigned to the same address. On write to TRBPR, a value is
written to the reload register, and on read from TRBPR, a counter value is read.
During a write to TRBPR the load timing from the reload register to the counter differs between
counting in progress and counting stopped. For details, see descriptions of each operating mode.
The initial values of TRBPR and the counter are H'FF.