Datasheet

Section 14 Timer RB
REJ09B0465-0300 Rev. 3.00 Page 425 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
14.2.4 Timer RB Mode Register (TRBMR)
b7
TCKCUT
0
b6
0
b5
0
b4
0
b3
TWRC
0
b2
⎯
0
b1
0
b0
0
H'FFFFA3
TMOD[1:0]TCK[2:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 TCKCUT*
1
Count source
cutoff
0: Timer RB clock source is supplied.
1: Timer RB clock source is cut off.
R/W
6 to 4 TCK[2:0]*
1
Count source
select
000: φ
001: φ/8
010: Underflow of timer RA
011: φ/2
100: φ4
101: φ/32
110: φ/64
111: φ/128
R/W
3 TWRC Write control 0: Both the reload register and counter are written to.
1: Only the reload register is written to.
2 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
1, 0 TMOD[1:0]*
2
Operating
mode select
00: Timer mode
01: Programmable waveform generation mode
10: Programmable one-shot generation mode
11: Programmable wait one-shot generation mode
R/W
Notes: 1. A count source should not be switched or cut off during counting. The count source
should be switched or cut off when both the TSTART and TCSTF bits in TRBCR are 0
(when the timer counting is stopped).
2. An operating mode should be selected when the counting is stopped (when both the
TSTART and TCSTF bits in TRBCR are 0).
• TWRC bit (write control)
Controls the timing when the counter reflects the value of the reload register. This bit should
be 1 except in timer mode.