Datasheet

Section 13 Timer RA
Page 418 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
13.4 Usage Notes
1. The prescaler and timer are read out per byte inside the microcomputer even when they are
read out in 16-byte unit. Therefore, the timer value can be updated while those two registers
are read out.
2. The TEDGF and TUNDF bits in TRACR used in pulse width and pulse cycle measurement
modes assume the value 0 when 0 is written by a program and do not change if 1 is written. If
one flag is set to 0 by a program, use the MOV instruction to write 1 to the other flag. In this
manner, unintended flag changes can be prevented.
3. When a transition is made to pulse width or pulse cycle measurement mode from another
mode, the TEDGF and TUNDF bits are undefined. Timer RA counting should be started by
writing 0 to the TEDGF and TUNDF bits.
4. In some cases, the TEDGF bit becomes 1 on the first timer RA prescaler underflow signal that
is generated after the start of counting.
5. When using the pulse cycle measurement mode, set the TEDGF bit to 0 by allowing a length
of time 2 cycles or greater of the timer RA prescaler after the counting process is started.
6. After 1 is written to the TSTART bit when counting is stopped, the TCSTF bit remains 0 for
the number of cycle of count source. Registers associated with the timer RA except the
TRACR for reading should not be accessed until the TCSTF bit becomes 1. Counting starts
from a valid edge of the first count source after the TCSTF bit becomes 1.
After 0 is written to the TSTART bit when counting is in progress, the TCSTF bit remains 1
for the number of cycle of count source. Registers associated with the timer RA except the
TRACR for reading should not be accessed until the TCSTF bit becomes 0. Counting stops
when the TCSTF bit becomes 0.
7. When writing successively to TRAPRE during counting (TCSTF=1), allow at least four cycles
of the clock source for counting as the minimum interval for writing.
8. When writing successively to TRATR during counting (TCSTF=1), allow at least four cycles
of the clock source for counting as the minimum interval for writing.
9. When values for TRAPRE and TRATR are successively read out from the same register, allow
at least two cycles of the clock source for counting as the minimum interval for reading.