Datasheet

Section 13 Timer RA
REJ09B0465-0300 Rev. 3.00 Page 415 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
13.3.6 Pulse Cycle Measurement Mode
This mode measures the cycle of external pulses that are input from the TRAIO pin. Setting the
TMOD[2:0] bits in TRAMR to B'100 activates the pulse cycle measurement operation. The
TEDGSEL in TRAIOC can be used to specify whether the period from the falling edge to another
falling edge of the input pulse of the TRAIO pin is to be measured or the period from the rising
edge to another rising edge is to be measured. Setting the TIPF[1:0] bits in TRAIOC also enables
to apply a filter to external pulse input. Count sources are selected using the TCK[2:0] bits in
TRAMR.
After the start of timer counting, each time a valid input edge is input from the TRAIO pin, a value
is transferred from the counter of the timer RA to the read buffer in synchronization with the
underflow of the timer RA prescaler. The value in the read buffer is retained until the timer RA
register is read. Also, after a value is transferred to the read buffer, a value is transferred from the
reload register to the counter in synchronization with the next underflow of the timer RA
prescaler. Reading of the read buffer should not be performed until the TEDGF bit in TRACR is
set to 1. An interrupt request is generated either when the TEDGF bit in TRACR is set to 1 or
when the timer RA counter underflows.
For pulse input to the TRAIO pin, pulses with a cycle greater than double the cycle of the timer
RA prescaler should be input. Also, input pulses for which the high pulse width and the low pulse
width are greater than the cycle of the timer RA prescaler. If pulses with a short cycle are input,
the input is ignored in some cases.
Figure 13.4 shows an operation example of pulse cycle measurement mode.