Datasheet

Section 13 Timer RA
Page 412 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
H'01 H'01H'06 H'04H'05 H'03 H'02
H'03
H'01 H'00 H'00 H'01 H'00 H'01 H'00
H'25H'02
H'24
Count source
Reload register for
timer RA prescaler
Counter for
timer RA prescaler
Reload register
for timer RA
Timer RA counter
TRAIF in TRAIR
"0"
Write H'01 to TRAPRE and
H'25 to TRATR by a program
After a write, reload register is written to
after four counts of count source.
Previous value New value (H'01)
Previous value
New value (H'25)
Reloaded at the second underflow
IR bit does not change until an underflow occurs with
the new value.
Reload register is written to
at the first underflow after a write.
Reloaded at the
second count
source
Reloaded on
underflow
Figure 13.2 Rewriting Count Value When Timer RA Counting is in Progress
13.3.2 Timer Mode
This mode counts internal clocks as a count source. Setting the TMOD[2:0] bits in TRAMR to
B'000 activates the timer mode operation. A count source is selected in terms of the TCK[2:0] bits
in TRAMR.
13.3.3 Pulse Output Mode
This mode counts internal clocks as a count source, and toggle-outputs pulses from the TRAIO pin
each time the counter underflows. Setting the TMOD[2:0] bits in TRAMR to B'001 activates pulse
the output mode operation. A count source is selected using the TCK[2:0] bits in TRAMR. The
initial output value of the pin is set using the TEDGSEL bit in TRAIOC. By setting the TOENA
bit in TRAIOC, a reverse output can be output from the TRAO pin to the TRAIO pin.