Datasheet

Section 13 Timer RA
REJ09B0465-0300 Rev. 3.00 Page 407 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
13.2.3 Timer RA Mode Register (TRAMR)
b7
TCKCUT
0
b6
0
b5
0
b4
0
b3
⎯
0
b2
0
b1
0
b0
0
H'FF06F2
TCK[2:0] TMOD[2:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 TCKCUT Timer RA count
source cutoff
0: Count source is supplied.
1: Count source is cut off.
R/W
6 to 4 TCK[2:0] Timer RA count
source select
000: φ
001: φ/8
010: Setting prohibited
011: φ/2
100: φsub
101: φ/32
110: φ/64
111: φ/128
R/W
3 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
2 to 0 TMOD[2:0] Timer RA
operating mode
select
000: Timer mode
001: Pulse output mode
010: Event count mode
011: Pulse width measurement mode
100: Pulse cycle measurement mode
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
R/W
Note: The counting should be stopped (when both the TSTART and TCSTF bits in TRACR are 0)
when this register is modified.
• TCK2 bit and TCK0 bit (timer RA count source select)
A count source is selected if the mode is not the event count mode.
• TMOD2 bit to TMOD0 bit (timer RA operating mode select)
Writing to TRAMR initializes the output level.