Datasheet

Section 13 Timer RA
Page 406 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
0 TEDGSEL Input/output
polarity switch
• Timer mode
This bit should be set to 0.
• Pulse output mode
0: The initial value of TRAIO output is set at a high
level.
1: The initial value of TRAIO output is set at a low
level.
• Event count mode
0: Counter incremented at the TRAIO input rising
edge. The initial value of TRAIO output is set at a
low level.
1: Counter incremented at the TRAIO input falling
edge. The initial value of TRAIO output is set at
a high level.
• Pulse width measurement mode
0: Measures the low-level width of TRAIO input.
1: Measures the high-level width of TRAIO input.
• Pulse cycle measurement mode
0: Measures from the rising edge of the
measurement pulse to the next rising edge.
1: Measures from the falling edge of the
measurement pulse to the next falling edge.
R/W
Note: When TCSTF = 1, do not rewrite this register.
• TIOGT1 bit and TIOGT0 bit (TRAIO event input control 1 and 0)
These bits control input events in event counter mode.
• TIPF1 bit and TIPF0 bit (TRAIO input filter select 1 and 0)
If filtered operation is selected, the input is determined when the same value is sampled three
times in succession from the TRAIO pin.