Datasheet

Section 13 Timer RA
REJ09B0465-0300 Rev. 3.00 Page 405 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
13.2.2 Timer RA I/O Control Register (TRAIOC)
b7
0
b6
0
b5
0
b4
0
b3
TIOSEL
0
b2
TOENA
0
b1
TOPCR
0
b0
TEDGSEL
0
H'FF06F1
TIOGT[1:0] TIPF[1:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7, 6 TIOGT[1:0] TRAIO event
input control
00: Input control is not performed.
(Events are always enabled.)
01: Input control is performed.
(Events are enabled when IRQ2 input is high.)
10: Setting prohibited
11: Setting prohibited
R/W
5, 4 TIPF[1:0] TRAIO input
filter select
00: No filter operation
01: Filtered (Sampled at φ)
10: Filtered (Sampled at φ/8)
11: Filtered (Sampled at φ/32)
These bits should be set to B'00 in timer mode and
pulse output mode.
R/W
3 TIOSEL TRAIO input
select
0: Input from the TRAIO pin
1: Input from the LIN
R/W
2 TOENA TRAO output
enable
0: TRAO outputs are disabled.
1: TRAO outputs are enabled.
This bit should be set to 0 except in event counter
mode and pulse output mode.
R/W
1 TOPCR TRAIO output
control
0: TRAIO outputs are enabled.
1: TRAIO outputs are disabled.
This bit should be set to 0 except in pulse output
mode.
R/W