Datasheet

Section 13 Timer RA
REJ09B0465-0300 Rev. 3.00 Page 403 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
13.2.1 Timer RA Control Register (TRACR)
b7
⎯
0
b6
⎯
0
b5
TUNDF
0
b4
TEDGF
0
b3
⎯
0
b2
TSTOP
0
b1
TCSTF
0
b0
TSTART
0
H'FF06F0
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7, 6 ⎯ Reserved These bits are read as 0. The write valued should be 0. ⎯
5 TUNDF Timer RA
underflow flag
[Setting condition]
• When timer RA underflows from H'00 to H'FF.
[Clearing condition]
• When 0 is written to this bit*
R/W
4 TEDGF Valid edge
detection flag
[Setting conditions]
• When the pulse width measurement is completed
with TSTART in TRACR = 1, in pulse width
measurement mode.
• When the timer RA prescaler underflows at the
second time after a valid edge of the measurement
pulse is input, in pulse cycle measurement mode.
[Clearing condition]
• When 0 is written to this bit*
R/W
3 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
2 TSTOP Timer RA
count forced
stop
0: Timer RA counting is continued.
1: Timer RA counting is forcedly stopped.
R/W