Datasheet

Section 12 Event Link Controller
REJ09B0465-0300 Rev. 3.00 Page 387 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
12.2.13 Event-Generation Timer Delay Selection Register (ELTMDR)
b7
0
b6
0
b5
0
b4
0
b3
0
b2
0
b1
0
b0
0
H'FF06BB
C3DLY[1:0] C2DLY[1:0] C1DLY[1:0] C0DLY[1:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7, 6 C3DLY[1:0] Channel 3
delay select
00: No delay
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
R/W
5, 4 C2DLY[1:0] Channel 2
delay select
00: No delay
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
R/W
3, 2 C1DLY[1:0] Channel 1
delay select
00: No delay
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
R/W
1, 0 C0DLY[1:0] Channel 0
delay select
00: No delay
01: 1 clock cycle
10: 2 clock cycles
11: 3 clock cycles
R/W
Note: When clock source φELC/1 is selected as an event-generation interval in ELTMSA or
ELTMSB, there is no delay regardless of settings of the above bits.
ELTMDR determines the necessary delay time, which is the time from the specified event-
generation timing (= interval) to the actual generation timing of the event in terms of the cycles of
the selected clock source.